1. Field
The present disclosure generally relates to memory devices. More specifically, the present disclosure relates to a circuit that transfers charge between memory devices when transitioning one of the memory devices from an active operating mode to a standby mode.
2. Related Art
Power consumption in memory devices, such as static random access memories (SRAM), is increasing. For example, as critical dimensions decrease in size to 32 or 45 nm, the leakage current in SRAM and its reliability are becoming significant design problems. Additionally, modern microprocessors typically include a large amount of embedded memory (for example, up to 32 MB in a level 3 cache), which increases the leakage current because most of the SRAM cells in this embedded memory spend a significant amount of time in a standby mode.
To reduce the leakage current, voltage control is often used in an SRAM cell during a read cycle (this voltage control is sometimes referred to as ‘read assist’). In particular, during a standby mode the SRAM-cell voltage is in a lower voltage domain (VCS_l. Then, during a read cycle the SRAM-cell voltage is transitioned to a higher voltage domain (VCS_h). While read assist reduces the leakage current, it can waste power because during a read cycle the large capacitance associated with an SRAM cell is charged up to VCS_h, which is subsequently dumped into VCS_l during a precharge cycle.
To address this problem, in some SRAM cells a portion of this charge is recycled or transferred into a bit line (for use during the precharge cycle), and the remaining charge is dumped into ground. However, this technique may not be practical for high-performance embedded memory because the bit-line discharge is relatively small in comparison to the total charge. Consequently, most of the charge is dumped into ground, and little or no charge is recycled. This wasted power increases as the number of SRAM cells connected to each bit line increases (such as in high-performance embedded memory) because more charge is needed to increase the SRAM-cell voltage from VCS_l to VCS_h during a read-assist operation. In particular, the charge equals Cmem·(VCS_h−VCS_l, where Cmem is the memory power capacitance, which includes the SRAM-cell power-wire capacitance and the SRAM-cell junction/gate capacitance.
Hence, what is needed are memory devices without the problems described above.